3.3v/2.5v 1:9 lvcmos clock fanout buffer motorola semiconductor technical data order number: MPC9447/d rev 2, 04/2003 ? motorola, inc. 2003 3.3v/2.5v1:9lvcmosclock the MPC9447 is a 3.3v or 2.5v compatible, 1:9 clock fanout buffer targeted for high performance clo ck tree applications. with output frequencies up to 350 mhz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. features ? 9 lvcmos compatible clock outputs ? 2 selectable, lvcmos compatible inputs ? maximum clock frequency of 350 mhz ? maximum clock skew of 150 ps ? synchronous output stop in logic low state eliminates output runt pulses ? high--impedance output control ? 3.3v or 2.5v power supply ? drives up to 18 series terminated clock lines ? ambient temperature range --40 _ cto+85 _ c ? 32 lead lqfp packaging ? supports clock distribution in networking, telecommunications, and computer applications ? pin and function compatible to mpc947 functional description MPC9447 is specifically designed to distribute lvcmos compatible clock signals up to a frequency of 350 mhz. each output provides a precise copy of the input signal with a near zero skew. the outputs buffers support driving of 50 ? terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. two selectable independent lvcmos compatible clock inputs a re available, providing support of redundant clock source systems. the MPC9447 clk_stop control is synchronous to the fa lling edge of the input clock. it allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. applying the oe control will force the outputs into high--impedance mode. all inputs have an internal pull--up or pull--down resistor pre venting unused and open inputs fro m floating. the device supports a 2.5 vo r 3.3 vpowe rsuppl yan da nambien ttemperatur erang eo f--4 0_c to +85_c .th empc944 7i spi nan dfunctio ncompatible bu tperformanc e--enhance dt oth empc947. fasuffix 3 2--lea dl qf pp acka ge cas e873a 3.3 v/2.5 v lvcmos 1:9 clock fanout buffer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet MPC9447 idt? 3.3v/2.5v 1:9 lvcmos clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MPC9447 1
idt? 3.3v/2.5v 1:9 lvcmos clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MPC9447 2 MPC9447 3.3v/2.5v 1:9 lvcmos clock fanout buffer netcom MPC9447 motorola timing solutions 2 gnd q2 vcc q1 gnd q0 vcc gnd gnd q6 vcc q7 gnd q8 vcc gnd gnd q3 vcc q4 gnd q5 vcc gnd gnd clk_sel cclk0 cclk1 clk_stop oe vcc gnd 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 MPC9447 figure 1. logic diagram figure 2. 32--lead pinout (top view) 0 1 cclk0 cclk1 clk_sel clk_st op oe q0 q1 q2 q3 q4 q5 q6 q7 q8 v cc v cc v cc clk stop sync (all input resistors have a value of 25k ! ) table 1. function table control default 0 1 clk_sel 1 clk0 input selected clk1 input selected oe 1 outputs disabled (high--impedance state) a outputs enabled clk_st op 1 outputs synchronously stopped in logic low state outputs active a. oe = 0 will high--impedance tristate all outputs independent on clk_st op table 2. pin configuration pin i/o type function cclk0 input lvcmos clock signal input cclk1 input lvcmos alternative clock signal input clk_sel input lvcmos clock input select clk_st op input lvcmos clock output enable/disable oe input lvcmos output enable/disable (high--impedance tristate) q0--8 output lvcmos clock outputs gnd supply ground negative power supply (gnd) v cc supply v cc positive power supply for i/o and core. all v cc pins must be connected to the positive power supply for correct operation table 3. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
idt? 3.3v/2.5v 1:9 lvcmos clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MPC9447 3 MPC9447 3.3v/2.5v 1:9 lvcmos clock fanout buffer netcom MPC9447 timing solutions 3 motorola table 4. absolute maximum ratings a symbol characteristics min max unit condition v cc supply voltage -0.3 3.9 v v in dc input voltage -0.3 v cc +0.3 v v out dc output voltage -0.3 v cc +0.3 v i in dc input current table 5. dc characteristics (v cc =3.3v symbol characteristics min typ max unit condition v ih input high voltage 2.0 v cc +0.3 v lvcmos v il input low voltage -- 0 . 3 0.8 v lvcmos v oh output high voltage 2.4 v i oh =-24ma a v ol output low voltage 0.55 0.30 v v i ol =24ma i ol =12ma z out output impedance 17 ! i in input current b ? ? ? table 6. ac characteristics (v cc =3.3v symbol 5characteristics min typ max unit condition f ref input frequency 0 350 mhz f max output frequency 0 350 mhz f p, r e f reference input pulse width 1.4 ns t r ,t f cclk0, cclk1 input rise/fall time 1.0 b ns 0.8to2.0v t plh/hl propagation delay cclk0 or cclk1 to any q 1.3 3.3 ns t plz, hz output disable time 11 ns t pzl, zh output enable time 11 ns t s setup time cclk0 or cclk1 to clk_stop c 0.0 ns t h hold time cclk0 or cclk1 to clk_stop c 1.0 ns t sk(o) output-to-output skew 150 ps t sk(pp) device-to-device skew 2.0 ns t sk(p) dc q output pulse skew d output duty cycle f q <170 mhz 45 50 300 55 ps % dc ref = 50% t r ,t f output rise/fall time 0.1 1.0 ns 0.55 to 2.4v t jit(cc) cycle-to-cycle jitter rms (1 ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
idt? 3.3v/2.5v 1:9 lvcmos clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MPC9447 4 MPC9447 3.3v/2.5v 1:9 lvcmos clock fanout buffer netcom MPC9447 motorola timing solutions 4 table 7. dc characteristics (v cc =2.5v symbol characteristics min typ max unit condition v ih input high voltage 1.7 v cc +0.3 v lvcmos v il input low voltage -0.3 0.7 v lvcmos v oh output high voltage 1.8 v i oh =-15 ma a v ol output low voltage 0.6 v i ol =15ma z out output impedance 19 ! i in input current b ? ? ? table 8. ac characteristics (v cc =2.5v symbol characteristics min typ max unit condition f ref input frequency 0 350 mhz f max output frequency 0 350 mhz f p, r e f reference input pulse width 1.4 ns t r ,t f cclk0, cclk1 input rise/fall time 1.0 b ns 0.7to1.7v t plh/hl propagation delay cclk0 or cclk1 to any q 1.7 4.4 ns t plz, hz output disable time 11 ns t pzl, zh output enable time 11 ns t s setup time cclk0 or cclk1 to clk_stop c 0.0 ns t h hold time cclk0 or cclk1 to clk_stop c 1.0 ns t sk(o) output-to-output skew 150 ps t sk(pp) device-to-device skew 2.7 ns t sk(p) dc q ouput pulse skew d output duty cycle f q <350 mhz 45 50 200 55 ps % dc ref = 50% t r ,t f output rise/fall time 0.1 1.0 ns 0.6to1.8v t jit(cc) cycle-to-cycle jitter rms (1 ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9447 timing solutions 5 motorola application information figure 3. output clock stop ( cl k _ stop ) timing diagram cclk0 or cclk1 clk_stop q0 to q8 driving transmission lines the MPC9447 clock driver was designed to drive high speed signals in a terminated transmission line environment. to provide the optimum flex ibility to the user, the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of 17 ? ? figure 4. single versus dual transmission lines 17 ? in MPC9447 output buffer r s =33 ? z o =50 ? outa 17 ? in MPC9447 output buffer r s =33 ? z o =50 ? outb0 r s =33 ? z o =50 ? outb1 this technique draws a fairly high level of dc current and thus only a single terminated line can be driven by each output of the MPC9447 clock driver. for the series terminated case, however, there is no dc current draw; thus, the outputs can drive multiple series terminated lines. figure 4 ?single versus dual transmission lines? illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when taken to its extreme, the fanout of the MPC9447 clock driver is effectively doubled due to its capability to drive multiple lines at v cc =3.3v. figure 5. single versus dual line termination waveforms time (ns) voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 101214 outb t d = 3.9386 outa t d = 3.8956 in the waveform plots in figure 5 ?single versus dual line termination waveforms? show the simulation results of an output driving a single line versus two lines. in both cases, the drive capability of the MPC9447 output buffer is more than sufficient to drive 50 ? ? ? ? ? ? ? ? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . idt? 3.3v/2.5v 1:9 lvcmos clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MPC9447 5 MPC9447 3.3v/2.5v 1:9 lvcmos clock fanout buffer netcom
idt? 3.3v/2.5v 1:9 lvcmos clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MPC9447 6 MPC9447 3.3v/2.5v 1:9 lvcmos clock fanout buffer netcom MPC9447 motorola timing solutions 6 are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. figure 6. optimized dual line termination 17 ? MPC9447 output buffer r s =16 ? z o =50 ? r s =16 ? z o =50 ? ? ? k 16 ? ? k 50 ? ? ? the following figures illustrate the measurement re ference for the MPC9447 clock driver circuit figure 7. cclk MPC9447 ac test reference for v cc =3.3vandv cc =2.5v pulse generator z=50 ! r t =50 ? z o =50 ? r t =50 ? z o =50 ? MPC9447 dut v tt v tt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9447 3.3v/2.5v 1:9 lvcmos clock fanout buffer netcom MPC9447 timing solutions 7 motorola figure 8. propagation delay (t pd ) test reference figure 9. output--to--output skew t sk(lh, hl) the pin--to--pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device the time from the output controlled edge to the non--controlled edge, divided by the time between output controlled edges, expressed as a percentage v cc v cc 2 gnd v cc v cc 2 gnd v cc v cc 2 gnd t p t 0 dc=(t p - t 0 x 100%) v cc v cc 2 gnd v cc v cc 2 gnd t p(lh) cclk q x t f t r v cc =3.3v v cc =2.5v 2.4 1.8v 0.55 0.6v figure 10. output pulse skew (t sk(p) ) test reference figure 11. output duty cycle (dc) figure 12. output transition time test reference the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs t n t jit(cc) = | t n -- t n+1 | t n+1 figure 13. cycle--to--cycle jitter figure 14. setup and hold time (t s ,t h ) test reference v cc v cc 2 gnd v cc v cc 2 gnd cclk q x t sk(lh) t sk(hl) t p(hl) t sk(p) =|t plh -- t phl | t p(lh) t p(hl) v cc v cc 2 gnd v cc v cc 2 gnd t s cclk pclk clk_st op t h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . idt? 3.3v/2.5v 1:9 lvcmos clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MPC9447 7
idt? 3.3v/2.5v 1:9 lvcmos clock fanout buffer freescale timing solutions organization has been acquired by integrated device technology, inc MPC9447 8 MPC9447 3.3v/2.5v 1:9 lvcmos clock fanout buffer netcom MPC9447 motorola timing solutions 8 outline dimensions fa suffix lqfp package case 873a--03 issue b 12 ref d1 d/2 e e1 1 8 9 17 25 32 f f e/2 detail g base c1 c b b1 metal section f--f e seating plane rr2 _ (s) l (l1) 0.25 gauge plane a2 a a1 detail ad detail ad d1/2 e1/2 e/2 4x d 7 a d b a--b 0.20 h 0.1 c (1) _ 8x a, b, d a--b m 0.20 d c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b, and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed themaximumbdimensionbymorethan 0.08--mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion: 0.07--mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25--mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1--mm and 0.25--mm from the lead tip. dim min max millimeters a a1 7.00 bsc a2 0.80 bsc b 9.00 bsc b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 e e e1 l l1 1.00 ref r1 0.08 0.20 r2 s 1 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0 . 0 8 -- -- -- 07 __ _ 9.00 bsc 7.00 bsc 0.50 0.70 0.20 ref d 4x a--b 0.20 c d 6 6 4 4 detail g pin 1 index c 32x 28x h 5 8 plating 3 " " rr1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9447 3.3v/2.5v 1:9 lvcmos clock fanout buffer netcom mpc92459 900 mhz low voltage lvds clock synthesizer netcom ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future networks. contact: www.idt.com part numbers insert product name and document title netcom
|
